The present invention relates generally to flip-flop circuits. More particularly, the present invention relates to a low power flip-flop having a higher phase margin than conventional flip-flops utilized in digital data recovery circuits.
Flip-flop circuits are often utilized in the context of digital data/clock recovery schemes and, particularly, in phase detector arrangements employed in clock recovery circuits. Clock recovery circuits are used to obtain timing information from a digital signal that has been transmitted or communicated without a corresponding clock signal. Consequently, such flip-flop circuits may be used in any number of practical digital applications, e.g., SONET systems, ethernet systems, lightwave communication systems, hard drive reading systems, or the like.
A conventional flip-flop circuit 100 is illustrated in FIG. 1 as a simple block diagram. Flip-flop circuit 100 generally includes an input data buffer 102, an input clock buffer 104, a master latch circuit 106, and a slave latch circuit 108. Input buffers may be employed in such a flip-flop circuit because fan-out and slew rate affects the phase margin at high speeds. The basic operations of flip-flops, buffers, and latches are well known to those skilled in the art. Accordingly, such fundamentals are not described in detail herein. In accordance with known principles, flip-flop circuit 100 generates an output 116 of digital bits in response to an input 118 of digital bits and in response to a clock signal 109. Master latch 106 and slave latch 108 sample and hold the digital data in response to a master clock signal 112 and the slave clock signal 114.
Input data buffer 102 and input clock buffer 104 may function as amplifiers to suitably condition a digital input signal 118 and a digital clock signal 109, respectively (for purposes of this description, the various input and output signals are assumed to be digital signals). Input data buffer 102 is connected to a master data input of master latch circuit 106 such that the output of input data buffer 102 is associated with a master data input signal 110. Input clock buffer 104 produces master clock signal 112 (which may include a clock signal and an inverse clock signal), while slave clock signal 114 is in anti-phase with master clock signal 112. The output of master latch circuit 106 is connected to the data input of slave latch circuit 108. Slave latch circuit 108 generates output signal 116 in response to slave clock signal 114. In a practical embodiment, master data input signal 110, the output of master latch circuit 106, and output signal 116 are differential signals (the various figures may represent such differential signals with a single line).
FIG. 2 is a timing diagram that illustrates the sample and hold patterns associated with flip-flop circuit 100. Sample and hold periods for master latch circuit 106 respectively correspond with hold and sample periods for slave latch circuit 108. In flip-flop circuit 100, master latch circuit 106 switches from a sampling state to a holding state in response to the falling edge transition of master clock signal 112. As is well known to those skilled in the art, the differential clock signals enable master latch circuit 106 and slave latch circuit 108 to be clocked out of phase in a practical manner by reversing the positive and negative clock inputs. Similarly, master latch circuit 106 switches from a holding state to a sampling state in response to the rising edge transition of master clock signal 112. Due to the inverse nature of slave clock signal 114 relative to master clock signal 112, slave latch circuit 108 switches from a holding state to a sampling state in response to the falling edge transition of master clock signal 112 (i.e., the rising edge transition of slave clock signal 114) and switches from a sampling state to a holding state in response to the rising edge transition of master clock signal 112 (i.e., the falling edge transition of slave clock signal 114).
A xe2x80x9ccenteredxe2x80x9d setup hold data alignment 120 (for maximum decision margin) and a setup hold data alignment violation 122 are depicted in FIG. 2, where it is assumed that the internal flip flop delays are negligible or zero. xe2x80x9cDATAM INxe2x80x9d represents a stream of digital bits (e.g., bit values A, B, and C, where A, B, and C are either ones or zeros) present at the D input to master latch circuit 106. xe2x80x9cDATAM OUTxe2x80x9d represents a stream of digital bits present at the Q output of master latch circuit 106. Similarly, xe2x80x9cDATAS OUTxe2x80x9d represents a stream of digital bits present at the Q output of slave latch circuit 108. With respect to centered alignment 120, master latch circuit 106 transitions from sample to hold when the current DATAM IN value (bit A) is well settled, i.e., the input to master latch circuit 106 had plenty of time to settle to the current value near the beginning of the sample period. Thus, when slave latch circuit 108 begins sampling bit A, the output value held at master latch circuit 106 is well before the transition clock edge. The master sample to hold (and slave hold to sample) transition point is indicated by the dashed line 124.
In contrast to centered alignment 120, alignment violation 122 depicts a situation where flip-flop circuit 100 may encounter errors. A setup hold alignment violation may occur if master latch circuit 106 is changing from the sample state to the hold state while the input data is changing. The transition from master latch sample to master latch hold is indicated by the dashed line 126. At this time, the current DATAM IN value is changing from bit A to bit C. Consequently, the sample to hold transition may encounter a xe2x80x9cglitchxe2x80x9d because master latch circuit 106 is attempting to hold a bit value that may be changing, which in turn causes the input of slave latch circuit 108 to vary. Such a glitch or imperfection is depicted in the DATAM OUT pattern proximate transition point 126. If the change in the DATAM IN bit occurs at (or sufficiently near to) the transition point 126, then an output bit error may result because, in this example, the DATAS OUT bit can either be bit A or bit C. On the other hand, if the change in the DATAM IN bit does not occur at the transition point 126, then an output delay may occur while slave latch circuit 108 waits for the bit value at the output of master latch circuit 106 to stabilize. As the transition point 126 approaches the point where the DATAM IN bit value changes, the output delay increases until, eventually, a bit error occurs.
In addition, because both master latch circuit 106 and slave latch circuit 108 can be transparent (i.e., the latch input appears at the latch output) during the transition 126, the desired output edge of the output signal may be delayed due to finite slew rates. In phase detector applications, where the phase information is typically obtained by comparing the input of the master latch to the retimed data (e.g., the output of the master latch), this delay results in a phase measurement error.
The phase margin of flip-flop circuits can be defined as the phase range between the clock and data that does not cause a significant delay of the output relative to the corresponding delay when the clock and data are xe2x80x9ccenteredxe2x80x9d (as described above). The setup time can be defined as the time the necessary for the data to be valid before the clock edge transition point, while the hold time can be defined as the time necessary for the data to be valid after the clock edge transition point. In other words, a flip-flop circuit having a large phase margin is able to process data over a larger phase difference range. For example, an arbitrary failure point for a flip-flop circuit may be defined with respect to the increase in the data zero crossing edge displacement relative to the centered sample condition. This value may be designated at, e.g., three picoseconds, for a 10 gigabit per second (Gbps) application. Consequently, if the output delay associated with such an application exceeds the three picosecond limit, then the phase margin of the flip-flop circuit is considered to be violated.
In a practical embodiment, the centered condition may be considered to be a reference condition where the output delay is minimal or negligible for practical purposes. As the master latch sample to hold transition point moves toward the input data transition point, the output of the slave latch becomes increasingly delayed. Eventually, at a certain relative sample to hold transition point, the output delay exceeds the delay threshold, e.g., three picoseconds. At this point, the phase margin of the device has been exhausted. When the master latch sample to hold transition point coincides with the input data transition point (or when the two are sufficiently close to each other), the output may result in a decision error. For phase detector applications, the output delay criteria may be more stringent than the requirement associated with bit error rate. FIG. 12 depicts phase margin characteristics of several flip-flop circuits. For example, a conventional low power flip-flop circuit (represented by a characteristic plot 1202) may have a phase margin of approximately 228 degrees, relative to a three picosecond edge displacement threshold.
FIG. 3 is a graph that illustrates the phase margin and output delay issues. The vertical scale represents the differential output voltage of a practical flip-flop circuit where positive 0.35 volts represents a logic high and negative 0.35 volts represents a logic low. The output voltage may be a differential voltage generated by a practical latch circuit. The zero voltage value is defined as the logic threshold associated with the digital data. The horizontal scale represents time, in picoseconds. In the context of FIG. 3, the data output is transitioning from a logic high to a logic low; the graph illustrates the shift in the zero output crossover point as a function of clock phase relative to the input data. For a practical 10 Gbps system in which the bit period is only 100 picoseconds the practical tolerable shift in output edge delay is about three to four picoseconds.
At some normalized time, the slave latch of the flip-flop circuit is prompted to change its output from high to low. As time progresses, the output voltage of the flip-flop circuit decreases until it reaches the logic threshold of zero volts. Plot 302 represents the extreme case where the setup/hold time is violated, resulting in a bit error. As shown, no meaningful output change occurs with respect to plot 302. Plot 304 represents the output voltage versus time where the clock is approximately centered in the phase margin of the flip flop circuit. For plot 304, the relatively long setup time enables the master latch input data to be well settled before the master latch switches from the sample state to the hold state (see alignment 120 in FIG. 2). In contrast, a plot 306 represents the output voltage versus time where the setup time approaches the phase margin limit. For plot 306, the relatively short setup time results in an increased amount of output edge delay. When compared to plot 304, the output edge delay associated with plot 306 is approximately five picoseconds (the dashed lines in FIG. 3 identify this time delay). As described above, a five picosecond output delay may be associated with a failure of the flip-flop circuit operating at 10 Gbps.
One prior art solution that increases the phase margin of a flip-flop circuit involves the use of high power transistors in the master latch and/or the slave latch. Higher power transistors are capable of producing faster switching speeds and, therefore, shorter setup and hold times. Consequently, high power flip-flops can tolerate larger phase differences between the sample and hold clock transition relative to the input data transition. Unfortunately, a substantial power xe2x80x9cpenaltyxe2x80x9d is imposed to obtain such enhanced flip-flop performance. For example, a conventional flip-flop circuit may require only 80 mW to 100 mW of operating power, while a high power flip-flop circuit may require approximately 500 mW of operating power. This drastic increase in operating power may not be desirable in many practical applications that have limited power budgets and restrictions on the physical size of the flip-flop circuits.
A flip-flop circuit in accordance with the present invention can be employed in the context of a data/clock recovery circuit such that the adverse effects associated with the lack of tolerance between the input data and the sampling clock phase are reduced. The techniques of the present invention may be used to increase the phase margin associated with conventional flip-flop circuits without a substantial increase in operating power. The increased phase margin of an illustrative flip-flop circuit enables the circuit to perform in an enhanced manner to thereby increase the upper limit on the phase margin, which affects the jitter tolerance specification at high jitter frequencies above the PLL loop bandwidth limit. This results in more linear phase detector transfer curves.
The above and other aspects of the present invention may be carried out in one form by a flip-flop circuit having: a master latch circuit that includes a master data output and a master clock input, where the master latch circuit is configured to switch between a sample state and a hold state in response to a master clock signal present at the master clock input; a slave latch circuit having a slave data input operatively coupled to the master data output and a slave clock input, where the slave latch circuit is configured to switch between a sample state and a hold state in response to a slave clock signal present at the slave clock input; and a delay element configured to produce a timing delay between a sample-to-hold transition associated with the master latch circuit and a hold-to-sample transition associated with the slave latch circuit.